Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to providing for raising a dielectric field when forming dual-orientation self-aligned vias.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. Designers use self-aligned vias (SAVs) for process efficiency and to manufacture more dense devices.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art single-orientation, self-aligned via being formed between two metal layers. In order to form an integrated circuit device, a first layer ultra low dielectric constant (k) (i.e., first ULK layer 110a) material is deposited on a substrate 105. Metal features (150a, 150b) in the M1 metal layer are formed within the first ULK layer 110a. A carbon-doped silicon nitride sublayer 140 (e.g., NBLoK, a trademark of Applied Materials, Inc.) may be formed above the first ULK layer 110a. 
A second ULK layer 110b is formed above the sublayer 140. Further, an M2 metal feature 120 may be formed in the second ULK layer 110b. In many cases, a connection from the M2 feature 120 and the second M1 feature 150b is desired. As such, a via 130 is formed in the second ULK layer 110b to connect the M2 feature 120 and the second M1 feature 150b. The via 130 is formed as a single-orientation self aligning to the M2 feature 120.
One of the problems associated with this state-of-the-art design is that an increased process margin is required to prevent an inadvertent coupling of the via 130 with the first M1 feature 150a. This increased process margin interferes with the ability to create more densely populated integrated circuits. Another problem includes the fact that an interface diffusion path exists at the edge of the via 130 in the sublayer 140. In order to address these problems, designers have resorted to implementing dual-orientation self-aligning vias.
FIG. 2 illustrates a stylized cross-sectional depiction of a state-of-the-art dual-orientation, self-aligned via being formed between two metal layers. FIG. 2 illustrates a first ULK 110a deposited on a substrate 105. Metal features (150a, 150b) in the M1 metal layer are formed within the first ULK layer 110a. In contrast to FIG. 1, a hard mask layer 260 (e.g., tetraethyl orthosilicate (TEOS) layer) is formed over the first ULK 110a. The hard mask layer 260 is formed to reduce time dependent dielectric breakdown (TDDB). However, this may cause a degradation of RC. The hard mask layer 260 is provided to reduce the diffusion path of features (e.g., via) formed above the hard mask layer 260. Gaps in the hard mask layer 260 are formed above the M1 features 150a, 150b. A metal recess process is performed to create a gap in the hard mask layer 260. This process may leave a residue 250 of metal material on the sidewalls of the gaps of the hard mask layer 260.
A thicker carbon-doped silicon nitride sublayer 140 may be formed above the hard mask layer 260 and between gaps of the hard mask layer 260. A second ULK layer 110b is formed above the sublayer 140. Further, an M2 metal feature 120 may be formed in the second ULK layer 110b. A connection from the M2 feature 120 and the second M1 feature 150b is provided by forming a via 230 in the second ULK layer 110b. The via 230 is formed as a dual-orientation self aligning to the M2 feature 120. One orientation of the via 230 is self-aligned to the M2 feature 120, while the second orientation is self-aligned to the second M1 feature 150b. The critical dimension of the bottom portion of the via 230 is matched to dimension of the second M1 feature 150b to reduce overlay impact between the via 230 and the second M1 feature 150b. 
Although there is an improvement in the diffusion path problem in the dual-orientation via implementation, there are other problems associated with this design. For example, a portion of the via 230 lands on the hard mask, which may cause process errors. Further, the process margin has to be increased to accommodate the portion of the via 230 that would land on the hard mask. Therefore, the hard mask 260 is required to be sufficiently thick to prevent overflow problems. This causes difficulties in manufacturing smaller integrated circuit devices.
Further, using state of the art processes, it is difficult to properly recess the metal material (e.g., copper) of the M1 metal features on the side walls of the recess area. As such, the residue 250 of metal material remains in the recess area above the M1 metal features 150a, 150b. It would be desirable in the state of the art to have a process of efficiently and accurately manufacturing dual-orientation, self aligned vias while properly forming recess areas above metal features and reducing sidewall residue in hard masks.
The present disclosure may address and/or at least reduce one or more of the problems identified above.